The length of interconnects between and within microprocessor data paths in functional blocks has increased as integration density has increased in integrated circuits (ICs). Because interconnect capacitance per unit length increases rapidly with lateral dimension scaling, long point-to-point interconnects may cause performance and power bottlenecks in ICs.
Dynamic buses may replace static buses for speed-critical on-chip interconnects due to the increasing interconnect delays and reduced cycle times associated with successive technology generations. Dynamic CMOS interconnect drivers have been substituted for static CMOS drivers in high performance on-chip busses. For example, in busses having static drivers, when neighboring wires switch in opposite directions, e.g., from Vss to Vcc on one wire and from Vcc to Vss on the neighboring wire, the voltage swing on the parasitic capacitor that inherently exists between the two wires is not Vcc-Vss. Rather, the voltage swing seen by the parasitic capacitor is doubled to (Vcc-Vss)*2. Therefore the effective capacitance to ground seen by the wire is doubled, yielding a Miller Coupling Factor (MCF) of 2.0.
However, in busses having dynamic drivers, all wires may be reset to a pre-charge state (for example, Vss) in a pre-charge portion of the clock cycle, and then may either remain at that state or switch to an opposite state (Vcc in this example) in an evaluate portion of the cycle. Since all wires in the bus are pre-charged to the same state, two neighboring wires cannot switch in opposite directions from the pre-charge state during evaluation, and a maximum voltage swing on the terminals of the parasitic capacitor between the two wires will be (Vcc-Vss). The MCF is thereby reduced from 2.0 in static CMOS drivers to 1.0 in dynamic CMOS drivers, thereby reducing a large component of the wire's worst-case effective coupling capacitance.
Dynamic buses offer reduced interconnect delays over static buses due to the fact that the Miller coupling factor reduces from a worst-case scenario of 2 (for static buses) to 1. The reduced effective switching capacitance on dynamic buses may result in much lower delays. However, dynamic buses may consume considerable power even at low input switching activities (such as in microprocessor buses) because the switching activity now depends upon the state of the data.